{"product_id":"9780471429760","title":"Verilog Coding for Logic Synthesis","description":"Provides a practical approach to Verilog design and problem solving.\u003cbr\u003e * Bulk of the book deals with practical design problems that design engineers solve on a daily basis.\u003cbr\u003e * Includes over 90 design examples.\u003cbr\u003e * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.\u003cbr\u003e * Book is suitable for use as a textbook in EE departments that have VLSI courses","brand":"Wiley","offers":[{"title":"Default Title","offer_id":46261191835889,"sku":"9780471429760","price":175.95,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0674\/5433\/7265\/files\/9780471429760_p0.jpg?v=1774002454","url":"https:\/\/shop.barnesandnoble.com\/products\/9780471429760","provider":"Barnes \u0026 Noble","version":"1.0","type":"link"}